2 - biUcell Characteristics in SONOS NOR - type Flash Memory Cell with Recessed Channel Structure

The silicon-oxide-nitride-oxide-silicon (SONOS) device has been considering very promising candidate for future nonvolatile flash memory in terms of process compatibility with "oon"itio*f Compleirentary Metal Oxide Semiconductor (CMOS) technology, scalability, pnocess, prograrn/erase voltage, simplicity, and 2-bitlcell storage. To increase storage capacity_of a flash mernory, 2-bitlcell operation has be-n considering athactive.[ l ll] However, as device size is scaled down, the redistribution of injected charges in the storage iayer becomes important issue for the reliability ofthe reasonable multi-bit operation. According to ITRS r6admap, physical gate length needs to be longer than 140 nm to alleviate the redistribution problem in conventional planar charmel devices.[I2] To achieve 2-biVcell _in sub-100 nm regime without charge redishibution in the storage layer, localized charge happing method by using spacers fonned on both sides of the control gate was aaopted in planar channel flash memory devices.[6-8] However, it is very diflicult to achieve large t]ueshold voltage (Zs,) margin for 2-bitlcell in these devices as the gate length scales down to sub-100 nm. As a promising candidate for high-density 2-bitlcell SONOS flash menory cell, we reported a new cell structure by adopting spacer-type charge storage layer inside recessed channel region.[9-10] The bottom comer of the recessed region affects negatively Z6 margin for 2-bitlcell operation. Thus it-is ."!.rit"d to check the length effect of the spacer-type ni-tide sidewall formed vertically on the side surface of the recessed region on the 2,1 nargin for 2-bitlcell. We investigate prograrnming/erasing characteristics injecrcd charges density along vertical storage layer and surface potential along the effective channel by using channel hot Jlectron iniection (GHEI) and band{o-band hot hole injecrion (BtBHHI) methods for complete 2-bitlcell operation.